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Method and Arrangement for Testing Switch-Network Components

IP.com Disclosure Number: IPCOM000034285D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Tsui, FF [+details]

Abstract

In a parallel-processor system operating with packet-switching of messages, an essential part is the switch-network interconnecting the various processing and memory elements. This article describes a method for testing switch-network components at high speeds, and the design of test-messages to facilitate such testing. (Image Omitted) Principle of Test Method: Test-Data Loopback: To achieve near-at-speed (multiple-consecutive-cycle) testing, a basic concept of test-data loopback can be used, whereby (see in Fig. 1) the test-object's data-outputs (DOs) are fed back to its data-inputs (DIs). (Image Omitted) The storage-elements (latches) within the test-object capture the test-results at the end of each cycle; this, together with the loopback, allows the results to be used as new test-inputs for the next cycle.