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DIAGNOSIS of ARRAY Failures in a Self-Test Environment

IP.com Disclosure Number: IPCOM000034287D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Gupta, VP Patel, ST Waicukauski, JA [+details]

Abstract

An array diagnostic methodology is described for a self-test environment. Array defects are diagnosed using both logic test and array test. Logic test diagnosis is more efficient than array test diagnosis. By applying logic test before array test, most of the array defects are diagnosed using logic test. For array test diagnosis: A trace-back analysis identifies the minimum amount of logic that needs to be simulated. The significant events simulator only simulates logic that changes from one pattern to next pattern. No simulation is done for data-in lines. These considerations minimize simulation activity and thus improve performance. PROBLEM STATEMENT The device under consideration is a multi-chip module. The device uses the STUMPS structure for implementing self-test.