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Driving Method for FET Output-Type Horizontal Deflection Circuit

IP.com Disclosure Number: IPCOM000034291D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Idei, S Kobayashi, M [+details]

Abstract

The disclosed technique is a driving method for a horizontal deflection circuit. This method accomplishes low power dissipation, high reliability for drive pulse duty error, and smaller space occupation at a printed circuit board. A power MOSFET is used for the purpose of both switching device and dumper diode of horizontal deflection circuit. Its gate is driven by a push-pull emitter follower circuit to switch the FET to "On" and "Off" rapidly. The gate drive voltage must be held at a high enough voltage in the case of the FET "On" state in order to obtain the lowest Drain-Source saturation resistance, but drive duty or frequency error may happen due to some reason, such as ESD and logic failure, and a protection function must be provided.