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Switching-Time and MOS Transistor Size in Presence of Inductive Effects

IP.com Disclosure Number: IPCOM000034294D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
DeMicheli, G Ruehli, A [+details]

Abstract

The optimization of transistor widths or width/length ratios (w/l) for the minimization of propagation delay in static CMOS transistors is provided. The optimal w/l for a CMOS gate is found to be a function of the inductive effects introduced by power and ground busses as well as the capacitive and resistive loads, respectively introduced by the transistor, and the power and ground busses. Because induction increases with current, it is found, in contrast to the presently standard belief in the art, that it is not always possible to decrease propagation delay by increasing the current drive and w/l ratio of a CMOS transistor.