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Random Pattern Testing of LSSD Logic Devices by Multiple Sets of Weights

IP.com Disclosure Number: IPCOM000034302D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Eichelberger, EB Lindbloom, E Waicukauski, JA [+details]

Abstract

VLSI (very large-scale integrated) circuit chips are very difficult to give 100% test coverage to without incurring enormous test generation costs. By use of the algorithm described in this article, together with the application of [1, 2], weighted random pattern (WRP) testing is shown to have the capability of full (100%) test fault coverage in detecting faults in LSSD (level sensitive scan design) logic while achieving a significant reduction in the number of random patterns otherwise required to provide adequate test coverage. The use of weighted random stimuli to test LSSD logic devices [1] is a very powerful way of reducing the number of random patterns necessary to achieve an acceptable test.