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Modified Input/Output Bus Structure for High Speed Data Transfers Disclosure Number: IPCOM000034305D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

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Chorpenning, JS Leininger, JC McClurg, RA van den Berg, JW [+details]


A technique is described whereby an existing input/output (I/O) bus, as used in contemporary data processing systems, is modified to obtain high speed transfers. The concept utilizes a term "packet mode" to represent a direct interface between attached peripherals as well as between such peripherals and a host processing system, while coexisting with existing modes of data transfer. Described is an exemplary application, referencing the IBM Series/1; however, extensions to similar systems can apply. (Image Omitted) During the execution of an I/O instruction, an interval of time is dedicated to the execution of a "burst mode service gate capture sequence". (For details of this sequence, refer to IBM Series/1 - Machine Logic Diagram (MLD), Part Number - 1636491, Pg. A5320).