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Adder Architecture for Address Generation by a Direct Memory Access Controller

IP.com Disclosure Number: IPCOM000034309D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Peterson, GA [+details]

Abstract

A conventional Direct Memory Access (DMA) Controller transfers data between a memory location and an I/O port during one cycle. During each DMA cycle, the DMA Controller puts out the address of the memory location along with control information. The control information indicates which direction the data will be transferred and provides timing control. In a conventional DMA Controller design each channel consists of an Address Register, a Block Length Register, and a Control Register. When a given channel gets control, the Address Register and Block Length Register are loaded into an Address Counter and a Block Length Counter. The Address Counter counts up while the Block Length Counter counts down each time a piece of data is transferred. The DMA transfer is complete when the Block Length Counter reaches zero.