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Browse Prior Art Database

Trench Butted Lateral PNP Transistor

IP.com Disclosure Number: IPCOM000034320D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Hsieh, CM Huang, YS [+details]

Abstract

This article concerns a process for making a deep trench butted-free lateral PNP transistor (LPNP) having much lower parasitic PFET channel current than a conventional device employing polysilicon-filled deep trench isolation. The disclosed device can be made on a conventional NPN process line without need of additional masks or processes. (Image Omitted) The disclosed process involves diffusing an N-type dopant, e.g., phosphorus, into the trench polysilicon at the same time that the reach-through collector contact is formed. The P-type polysilicon in the trench is thus converted to N-type, producing about a 1-volt shift in the work function differential between the trench polysilicon and the base of the PNP transistor, while also gaining an orders-of- magnitude reduction in leakage. Figs.