Instruction With Long Operand Converted to Intermediate Length Operation by Central Processor
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
An instruction may (1) have the address and length of a variable-length operand specified in registers, (2) process the operand until an ending condition is met, (3) update the registers to show the address and remaining length when either the ending condition was met or the end of the operand was reached, and (4) set a condition code, which can control a branch instruction, to indicate whether or not the ending condition was met. The execution time of this instruction is proportional to the length of the part of the operand processed. An operation to be performed by a processor in a multiprocessor configuration may require that all other processors have stopped executing instructions.