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Improving Operational Performance of Cache Memories - Proper Handling of STORE Misses in Write-In Caches

IP.com Disclosure Number: IPCOM000034332D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Emma, PG Knight, JW Pomerene, JH Puzak, TR Rechtschaffen, RN [+details]

Abstract

A technique is described whereby the proper handling of store misses, in Write-In (WI) cache memories, improves the execution time of the STORE and reduces the need for special mechanisms to avoid operand store compare (OSC) operations. The improvement in cache memory operation involves, but is not limited to, situations where a STORE instruction creates storage activity that crosses a cache line boundary. In such circumstances, the upstream portion of the line, such as the portion of the line from the initial store to the end of the line, is irrelevant since it will be updated by the store. The trailing edge of the line will also, in such cases, be irrelevant to the STORE. Delays associated with the transferring of these double words (DWs) can delay the operation of the processor.