High-Speed Packet Switching Using an Auxiliary Tag Pipe
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
A technique is described whereby high-speed packet switching architecture uses an auxiliary tag pipe to indicate incoming data status so as to provide control of the communication switching process, thereby increasing processing speed. An efficient method of processing information to all hardware processing units is described so as to provide a hardware implementation for switching data frames and packets. The architecture is particularly suitable for implementation of lower layer bit-level protocol and can be applied to higher layer protocol processing. However, because of the high speed and simple implementation properties, the concept is considered ideal for general parallel processing. Telecommunication networks increasingly continue to handle high- speed data streams, so as to provide more advanced functions and services.