Hedge Fetch History Table
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
This article describes a technique to suppress hedge fetching in those cases where a performance advantage is identified. In a pipeline processor with a cache access time of two cycles, the major performance inhibitor is associated with taken branches and the instruction fetching associated with these branches. A significant performance improvement is derived from a Decode History Table (DHT) which predicts the action of conditional branches at decode time based on the last action of that branch. However, the contention for the cache port among operand accesses and instruction fetches creates a performance penalty when insufficient instruction fetching has been performed and the processor has no instruction to decode dynamic Instruction Buffer Empty (IBE).