Cross-Sectional Sample Preparation of Integrated Circuits for TEM Analysis, Using Kerfs of Adjacent Chips
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
A technique is described whereby cross-sectional transmission electron microscope (TEM) samples of integrated circuits can be produced quickly and reproduced, so as to retain large areas for examination. The concept is an improvement over the previous polishing and ion-beam milling techniques in that the kerfs of adjacent chips are used to reduce both the time required and the high failure rate of samples produced. Typically, cross-sectional TEM analysis of integrated circuits materials, as used in semiconductor-based manufacturing processes, is an integral part of process development and failure analysis. However, there is often a time lag between the end of processing and the return of results of the TEM analysis because of the tedious and exacting preparation required.