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Error Detection and Correction for 4-Bit-Wide Memories

IP.com Disclosure Number: IPCOM000034363D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Dennis, CA [+details]

Abstract

A novel code design is shown which detects and corrects the highest probable 4-bit-wide memory errors. Error detection and correction (EDC) is used to improve the effective reliability of a memory by detecting and correcting the most (Image Omitted) probable errors. Single bit Hamming EDC codes correct single-bit errors and can detect, without correcting, double-bit errors when an overall parity bit is appended to the word in storage. The predominate error mode for 1-bit wide memory chips is a soft or hard error in a single cell of a word in the storage array or a bit line failure. The next most likely error mode is due to an addressing error on the chip, a word line failure or a power failure on the chip. Both error modes manifest themselves as a single bit error.