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Charge Amplifying Dynamic Random Access Memory Cell Operation in the Two-Volt Range

IP.com Disclosure Number: IPCOM000034400D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Kenney, DM Thoma, EP [+details]

Abstract

Two techniques are described which provide good signal level from charge amplifying dynamic random access memory (DRAM) cells operated at two volts or less to preserve reliability of thin gate oxide. One technique is to operate the cell with pushed plate or storage node boosted. The other technique uses a modified charge amplifying cell having an added transistor, also operated with the pushed plate or boosted word line, providing capability to locally refresh storage node charge. (Image Omitted) Fig. 1 is a schematic of the charge amplifying DRAM cell (CACELL). Transistor T1 and T2 are P-channel field-effect transistors (FETs) having threshold voltage Vt = -2 volts for T1 and Vt = -1 volt for T2. Coupling ratio of node C to node RD (read line) is 2/3, i.e., a 3 volt transition on node RD causes a 2 volt change on node C.