Browse Prior Art Database

L2 Latch With Post Indication

IP.com Disclosure Number: IPCOM000034409D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Maley, GA McCabe, JF [+details]

Abstract

This article concerns the design of a post indicating latch (L2) circuit, having two different outputs, which can be employed to effectively eliminate a "short path" problem commonly encountered when optimizing the performance of large systems designed to the double register (L1/L2) concept. (Image Omitted) A typical double register (L1/L2) design is shown in Fig. 1. Overlapping the critical edges of the C1 and C2 clocks will act to increase system performance by decreasing cycle time but can result in a potential "short path" problem for some data paths. This design restraint occurs when a signal launched from an L2 latch catches up with data from the previous cycle by passing through a very short logic path in the combinational logic, thereby destroying the earlier data.