Single Clock CMOS Latch Compatible With Level-Sensitive Scan Design
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
A single clock CMOS latch for level-sensitive scan design (LSSD) compatibility is provided and comprises an input switch, a master stage and a slave stage. The timing and operation of the switch and stages is such that when the clock is active, the master stage is decoupled from the slave stage, new data is gated into the master, and a feedback path is enabled in the slave stage to hold the latch state. When the clock is inactive, a feedback path in the master stage is enabled, the feedback path in the slave is disabled, and new data proceeds to the output of the slave stage. The provided latch is free of races and provides LSSD compatibility. The provided latch is advantageous as opposed to the LSSD compatible latches of the prior art as the latches of the prior art require the use of two non-overlapping clocks.