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Scheme of Array Test Latch

IP.com Disclosure Number: IPCOM000034420D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Shen, MN [+details]

Abstract

Extremely accurate and balanced clock timings of high performance embedded arrays can be measured using the subject test latch. Referring to Fig. 1, a test latch is used between the array and the driver to latch the output data before going to the driver. An array data output signal can be used to set the latch and an external test clock signal can be used to prevent the latch from changing. The external test clock signal is connected in parallel through and-inverter logic gates AI1 and gates AI2 and AI3. AI1 is connected to the test latch enable T1 and AI3 is connected to test latch clock CLK. The rising edge of AI1 is now faster than the rising edge of AI3 thus balancing the output of the test latch independent of the initial start-up data input to the test latch.