Detailed ROUTING of Multiple Power and Ground Nets on a Single Layer
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
The problem of constructing a detailed routing of an arbitrary number of power, ground, and other I/O nets on a single layer is considered. The case where the number of such nets is two is discussed in . A rectangle called the chip boundary, enclosing a number of rectangles called the modules, is given. On the boundary of each module, a cyclic ordering of a set of terminals is given. A set of power, ground, and other I/O pads are placed on the boundary of the chip. Each pad corresponds to a distinct power, ground or I/O net. Each terminal on the modules is assigned to a specific net, and terminals in the same net are to be connected to its assigned pad. The placement of the modules, the positions of the terminals on the modules, and the positions of the pads on the boundary are all assumed given.