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TIMING-DRIVEN PARTITIONING OF PLAs

IP.com Disclosure Number: IPCOM000034440D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Ditlow, GS Raghavan, P [+details]

Abstract

When designing VLSI microprocessors, control logic such as op-decode is conveniently specified in PLA [1] form. For large fanout designs, such as op-decode, PLAs can be more suitable than random logic implementations since global wiring requirements are minimized. All internal wiring within a PLA is 100% wirable because of the regular PLA structure. The penalty for designs using PLAs is speed, since a two-level representation has a large number of product terms. Disclosed is a new algorithm which partitions a PLA into several smaller PLAs such that the timing is optimized. This differs from previous approaches [2, 3] to PLA partitioning which were based on minimizing PLA area.