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Automatic Testing Circuit for Combinational Logic

IP.com Disclosure Number: IPCOM000034441D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Millas, RJ Picon, RJ Robinson, WR Tate, JB [+details]

Abstract

A technique is described whereby a test circuit is added to level- sensitive scan design (LSSD) circuitry so as to provide a means to automatically test combinational logic which feeds input data to random-access memory (RAM) macros. The circuit eliminates the need to functionally test out scanning values through LSSD scan strings. Software can now be generated to provide a means to statically test the function. In prior art, testing of combinational logic circuitry required a functional testing procedure which required toggling the primary inputs with a tester to scan out the values through the LSSD scan strings. When a RAM macro is imbedded within a module, together with other logic, it becomes difficult to test the combinational logic feeding the inputs of the RAM macro.