Unified Simulation Using Flow Tables
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
There are predominantly two classes of simulators in use today -- switch level  and gate level . When simulating chips or large macros, a gate level representation is preferable for performance reasons since the simulation time is an order of magnitude faster than with a switch level representation. However, previous gate level representations have modeled Boolean behavior only and not the non-Boolean behavior of pass transistors . Described here is a generalized gate level simulator which uniformly simulates both gate level and switch level designs. This is accomplished by creating "flow tables"  from the design. Flow tables model the sequential behavior in precharged and charge sharing FET circuits. They are also useful in the analysis of latches implemented with gates.