Method to Automatically Generate Expects/Signatures for Testing
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Disclosed is method to generate functional speed test data considering device transition periods and high impedance periods. This method enables the manufacturing tester to compare expected values or generate a signatures only when the test point is at a stable 1 or 0 logic state. Problems due to "device under test" (DUT) variations are avoided. For instance, acceptable temperature, voltage, and semiconductor process variations are all factored into the manufacturing test data so that test results are insensitive to these variations. This method depends on a logic delay simulation with behavior models that know how to simulate the high impedance and transition state signal values. Physical models can be used to model off-the- shelf parts.