Output Timing Measurement in Physical Modeling
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Disclosed is a method for precisely measuring logic signal output timings from a real hardware device. A very similar technique can be used to precisely stimulate logic signal inputs or bidirectional signals. These precise timings are used in a logic simulator to verify the logic design or in a fault simulator to generate functional speed test data. The advantages of the disclosed method is accuracy and performance. Theoretically, the accuracy can be that of one primitive gate delay in the pin electronics integrated circuit. Simulation performance impact is negligible. A minimal embodiment employs logic enhancements to the typical pin electronics.