Latch Model Reduction Using Latch Behaviorals
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
An algorithm using minimized modelling of circuit latch parameters can be used to reduce CPU time and memory required for simulation and test generation of latches in LSSD (Level Sensitive Scan Design) circuits. The algorithm proposes using a more generalized entity, a latch behavior, to replace the latches in LSSD modelling. The algorithm defines a latch behavioral, as having clock data pairs as inputs, one output and a clock which must be set to a '1' for data to be captured in the latch. In the algorithm, when multiple clocks are activated simultaneously, clock dominance tables will predict the latch output resolution. The figure shows the flow chart of the algorithm. Step 1. Input Function Identification for LSSD Latches Tag blocks are used as part of the logic model.