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Cmos Receiver for Emitter-Coupled Logic Levels

IP.com Disclosure Number: IPCOM000034487D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Masenas, CJ [+details]

Abstract

A circuit is shown which converts emitter-coupled logic (ECL) signal levels to voltage levels capable of driving standard field-effect transistor (FET) circuits. The circuit disclosed is superior to prior art in speed, power consumption and tolerance to process parameter mismatches. Referring to the figure, a reference voltage VR is applied to the gates of the complementary transistor pair Q3 and Q4. Input voltage (VIN) is applied to the gates of Q1 and Q2. DC current flows through the string of transistors Q6, Q4, Q3 and Q5. This string of transistors provides the reference voltages seen at nodes N1 and N5 for the purpose of operating transistors Q1 and Q2 on the edge of conduction (where VR is approximately equal to VIN). It should be noted that the reference voltages generated are independent of the input voltage VIN.