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Vertical Deflection Circuit

IP.com Disclosure Number: IPCOM000034492D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Kobayashi, M [+details]

Abstract

Disclosed is a vertical deflection circuit which realizes a vertical deflection of a beam on a display surface in synchronism with a vertical synchronous signal of any frequency. Referring to the figure, an input terminal 5, to which a synchronous signal is applied, of a conventional vertical processing IC is opened, and the circuit shown is connected to input terminals 3, 4 and 6. When a vertical synchronous signal (V-SYNC) is held at a high or low voltage level, the base of the transistor Q1 is pulled down to a ground level by the resistor R2. The transistor Q1 is turned off, and current is not supplied from the transistor Q1 to trigger a self- oscillation of the circuit including a resistor R0, a capacitor C0, an amplifier OP1, a comparator CP1 and a bias voltage source.