Circuit to Accurately Determine Signal Development in a Read-Only Memory
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
A circuit is disclosed which simulates more of the actual delay path of a read-only memory (ROM) before switching an interlock and allows a better match for timing the signal development at the sense amplifier input. Also, mask shift discrepancies are eliminated. (Image Omitted) Prior art for timing ROM signal development only incorporated word line delays in circuit simulators. The disclosed circuit utilizes existing array structures and simulates word line delay, column line capacitance, bit line capacitance and array device size to track array signal development. The ROM circuit simulator represents either actual array structures or predetermined fractions of the actual array. The circuit uses a word line which is identical to that used in the array being simulated.