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Silicon, Elevated, Wireless Module Method for Making Engineering Changes

IP.com Disclosure Number: IPCOM000034507D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Kraus, CJ Stoller, HI Wu, LL [+details]

Abstract

A method has been developed for making high quality engineering changes (ECs) to multi-chip semiconductor modules without taking up excessive area. Silicon, Elevated, Wireless (SEW) technology is used in the proposal with buried EC lines connected to chip C4s. ECs are made by changing the appropriate chips, including wire direction, without using EC pads or jumper wires used. As the level of integration on chips increases, the opportunity to make an EC without changing at least one chip on the module is reduced. Previous technology required the use of top surface EC pads located around each chip on the multilayer ceramic (MLC) module. The pads were connected by discrete jumper wires to create the desired EC net. This technology will not be suitable for higher performance circuits of the future.