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Dynamic Random-Access Memory Refresh Using a Two-Cycle Direct Memory-Access Controller

IP.com Disclosure Number: IPCOM000034508D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Booth, JR Prutt, MA Scheibl, FJ [+details]

Abstract

Both bus cycles of a two-cycle DMA controller are utilized to periodically refresh dynamic random-access memories (RAMs). This prevents performance degradation due to such refresh. It is necessary to periodically refresh a dynamic RAM through using only a row address strobe (RAS) signal and not allowing a column address strobe (CAS) signal to become active. This enables each row of the dynamic RAM to be refreshed periodically. An Intel 80188 microprocessor has a two-cycle, two-channel DMA controller. Since the first of the two bus cycles of the direct memory-access (DMA) controller is used only to read and the second bus cycle only to write, there would be a significant degradation performance if only the read bus cycle were utilized for refresh.