Pipelined Processor Without Wait State
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
In CPU design, considerable performance improvement may be obtained by employing a pipelined architecture in which the various activities carried out in the processing of an instruction are confined to their own particular cycle. This allows a full cycle time of the 'pipeline clock' for the activity to be completed before the result is passed on to the next stage of pipeline. In a pipelined CPU design, a series of stages are controlled by a pipleline clock. When two instructions are interdependent, timing problems occur which are normally solved by introducing a wait state. This disclosure adds logic which allows the results from one cycle to be used immediately in the next cycle. Comparators enable a result to be made available early during an operand prefetch of the following instruction.