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Non-Destructive Method to Expose Plastic Packaged Semiconductor Chips for Failure Analysis Purposes

IP.com Disclosure Number: IPCOM000034532D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27

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Related People

Belami, C Cornier, JP Dumont, MF [+details]


It is very difficult to analyze semiconductor chips when embedded in plastic packages. The difficulty is raised because the insulation layers which passivate the chip and the packaging material itself are made of polyimide plastic which prohibits the use of any acid. As a result, etching the packaging material to expose the semiconductor chip could also destroy the insulation layers of the chip making the latter inoperative. The classical method is to polish manually the package from its top side. However, as the chip is not parallel to the top of the package (due to an erratic die-attach thickness), the risk of damaging the chip is quite high. The present method is based on parallel polishing the back side of the chip as it is the only reference plan.