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Test Generation for CMOS Stuck-Open Faults and Delay Faults Disclosure Number: IPCOM000034539D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27

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Hsieh, EP Wu, DM [+details]


Disclosed is a new test generation algorithm, for CMOS stuck-open faults and delay faults, which has the following advantages over the previous methods: 1. The fault model can be used for CMOS stuck-open faults, delay faults and DC stuck-faults. 2. The fault propagation algorithm uses a logic assignment method which is more relaxed than previous methods. This new technique accelerates the test generation speed, reduces the number of trackbacks and improves the test coverage. 3. The data compression technique used in this algorithm significantly reduces the test data volume for testing CMOS delay faults and stuck-open faults. 4.