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Method of Improving the Density of VLSI Chips by Using a Wiring Chip

IP.com Disclosure Number: IPCOM000034560D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Pollmann, K Schulz, U Wilczynski, J Zuehlke, R [+details]

Abstract

VLSI logic chips generally comprise two wiring metal layers. The density obtainable could be improved considerably by providing four such layers. However, there are technical problems, since the via hole technique yields poor channel pitches in the upper levels, say, 3.0 - 4.5 - 6.0 - 9.0 mm. Stud vias allow the same pitch for all layers, but the metallization process is very expensive. Therefore, a third and a fourth layer are provided in a separate wiring chip. This chip is produced by the standard 2-metal process and then soldered on top of the "normal" VLSI chip comprising the functional devices. The I/O circuits of silicon device chips are arranged along the chip periphery. After deposition of the second metal layer, the I/O circuits are provided with pads which allow testing and wire or tape bonding.