Method of Improving the Yield of VLSI Logic Chips by Using a Variable Wiring Channel Pitch
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
The wiring of VLSI logic chips is limited. For maximum gate density, such chips use the minimum wiring channel pitch that is technically feasible. A line width and spacing of, say, 1.2 and 1.3 mm, respectively, yield a wiring channel pitch of 2.5 mm. Automatic wiring programs permit using 60 to 70% of the wiring channels available. The distance between wires is constant, in the above example, amounting to 1.3 mm for neighboring wires and to 3.8 mm for wires between which there is an empty channel. This does not lead to optimum chip yield. Therefore, it is proposed that the space of an unused channel be allocated to the neighboring wires. The respective immediate neighbor is displaced 2 steps towards the unused channel, allowing the next wire to follow by 1 step. The proposed method is shown in Figs. 1A to 1C.