Complementary Decoder for Signal Line Boosting
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
By using N-well potential, wordlines are driven above the supply voltage (VDD). This complementary decoder circuit can be used in an N-type memory array configuration for low voltage (e.g., 3-volt) applications. Referring to the figure, output from a standard NOR decoder 2 goes through a set of inverter stages comprised of p-type transistor T3 and n-type transistor T4, through isolation device (low threshold transistor) T2 and driver device T1 (a second low threshold transistor) to a word line WL. The drain 4 of transistor T1 is connected to an N-well which is charged to a potential Vnw > VDD + VtT1 + VtTransfer, where VDD is the supply voltage, VtT1 is the threshold voltage of transistor T1, and VtTransfer is the threshold voltage of a transfer device (not shown).