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High Performance Totem-Pole Drive

IP.com Disclosure Number: IPCOM000034598D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Lundberg, MB Newton, SF [+details]

Abstract

Two MOSFET devices, which are arranged in a totem-pole configuration, have their gates capacitively coupled to a drive signal to minimize DC losses. Switching losses are minimized by using a parallel diode/ inductance in the gate drive circuit. The lower voltage level of the gate drive signal is translated to the high voltage level at the source of the MOSFET. (Image Omitted) A high current, high speed driver 1 (Fig. 1) inverts a logic signal having an amplitude of 5 volts and increases its amplitude to 15 volts. When the output of the driver 1 goes low upon receiving a positive input, it causes a MOSFET 2 to be turned on and a MOSFET 3 to be turned off. The MOSFET 2 has its source connected to +V, which is 45 volts, for example, and the MOSFET 3 has its drain connected to -V, which is -45 volts, for example.