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Random Pattern Test Strategy for Logic Surrounding Embedded Arrays

IP.com Disclosure Number: IPCOM000034665D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Forlenza, DO Waicukauski, JA [+details]

Abstract

The test strategy described in this article enhances random pattern testing of all logic peripheral to an embedded array. It does this by making all LSSD (level-sensitive scan design) patterns fully independent, thereby providing the ability to diagnose random pattern failures by post-test fault simulation plus an opportunity to use more efficient fault simulation techniques. Random pattern testing is increasingly employed in testing logic chips, especially those which are LSSD (level-sensitive scan design) [1]. Design tests already exist which provide for the complete and efficient random pattern test of LSSD logic chips 2, 3, 4.