Boolean Extraction From Transistors Circuits
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Since the design of VLSI chips is time-consuming and costly. getting a good design the first time is an economic imperative. Tools assessing the quality of what has been designed are valuable when the resources needed are easily usable. The Boolean Extractor finds out what the logical function of a network of transistors performs with a complexity factor which seems to be in O(h) (not proven). The algorithms have been implemented in VM/PROLOG which leads to effective graph traversing functions. The circuit is scanned from its output(s). The program tries to satisfy the conditions which turns the upward nodes active. When a primary input has to be set, the information is spread to the whole circuit (by unification mechanism).