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Chip on Board Device Registration Template Disclosure Number: IPCOM000034682D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue


Related People

Roody, AG Saraiya, MK Weber, JJ [+details]


Disclosed is the utilization of a template to retain silicon device location during chip on board (COB) attachment via standard surface mount processes. Silicon devices with solderable metals on the back side are attached to thermal carriers using standard surface mount processes. Subsequently, they are wirebonded to the carrier circuitry and encapsulated. During the solder reflow process, the devices float on the liquified solder diebond pad, allowing them to move, tilt, and skew. When the solder cools and solidifies, the devices are no longer positioned properly. In order to wirebond the devices with an automated wirebonder, the device position must be within certain limits for the vision system to recognize the pattern. These limits may vary with the equipment manufacturer.