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Method to Eliminate Function Table in Gate Level Simulator

IP.com Disclosure Number: IPCOM000034701D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Lemon, DS Vachon, MP Willis, SC [+details]

Abstract

The cycle time of a gate level simulator is typically limited by the access times of the various arrays used in the simulation processor. To determine the output of a gate that is to be simulated, most gate level simulators look up the result of the function in a function table. An example of this method is shown in Fig. 1. If the functions are defined in a particular manner, the need for a function table memory and its associated access time can be eliminated. The way in which the functions should be defined for a two input gate system in order to minimize the circuitry needed to realize the functions (results can be extended for more than two input gates) is shown in the chart in Fig. 2. The chart in Fig. 2 shows all of the possible functions and inputs for a two input gate.