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Substrate-Mounted Low Inductance Capacitor for Integrated Circuits

IP.com Disclosure Number: IPCOM000034712D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Oberschmidt, JM [+details]

Abstract

The presented technique provides low inductance capacitors to decouple three or four power supplies from each other and to reduce noise. Capacitors are mounted on substrates, near the integrated circuit chips, with solder ball connections, similar to chip attachment. The design consists of three electrode patterns 1, 2, and 3, with tabs 4 to facilitate connection between dielectric layers. Tabs 4 come to the surface of the stack 5 where plates of the same configuration can be electrically connected by shorting bars 6, which are contacted by a sequence of metals that adhere and are solder wettable. The same solder is used to join the completed capacitor unit to the substrate. The present design has only three electrode patterns 1,2, and 3, which will permit decoupling of three power supplies from each other.