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Efficient Software Allocation Scheme Disclosure Number: IPCOM000034730D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27

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Blades, JA Lambeth, SM Nordstrom, GM Prissel, LP Ziemba, RJ [+details]


This scheme is based on the ANSI (American National Standards Interchange) IPI-3 physical architecture, details of which are available to the public from the National Bureau of Standards, Washington, D.C. This scheme allocates and de-allocates hardware resources required by an input/output processor (IOP) interfacing to IPI-3 devices. The allocation scheme attempts to maximize the use of the IOP's hardware resources when multiple devices are connected to the same IOP. Fig. 1 represents the logical connection between the Processor Unit (PU), IOP and the IPI-3 type devices. To maximize an IOP's hardware resource usage in an environment where concurrent device activity and contention for the IOP's DMA (Direct Memory Access) resources (DMA posts) exist, the following sequence of events should occur: 1.