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Method Useful in Failure Analysis Which Provides Excellent Visibility on Trench Sidewalls

IP.com Disclosure Number: IPCOM000034753D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Merlot, F [+details]

Abstract

This failure analysis technique allows examination of the silicon lying on trench sidewall edges without etching the silicon in order to reveal potential defects. This technique could be applied to any semiconductor products embedding trench isolated transistors. The layer opposite silicon should be made of an oxide. The transistors isolated by polysilicon filled trenches are commonly used today. The transistors are isolated by a 2 m wide and 4.5 m deep trench. The trench is filled up with polysilicon, the polysilicon/silicon interface being comprised of 3000 Ao of silion oxide and silicon nitride. The sample is prepared as follows: - Deoxidize the sample by etching in a hydrogen fluoride solution (for 30 minutes). During this step, oxide and nitride layers on the trench sidewalls are selectively etched.