Multiphase LSSD Clock Generation and Distribution
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Problems associated with the design of logic employing multiphase LSSD clocks are unpredictable maximum transit time for paths between latches in different phases and efficiency of clock distribution. This disclosure addresses these problems by using a single clock and clock steering latches to create multiple clocks and to simplify clock distribution through the use of binary-encoded gating signals. LSSD (Level Sensitive Scan Design) is described in detail by U.S. Patents 3,761,695, 3,783,254 and 3,784,907. A simple generalized two-phase clocked LSSD design is shown in Fig. 1. The two phases of clocks could be used to drive two basically separate, but related functional islands of logic.