Modified Bus Arbitration for Rapid Interrupt Servicing
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
When building a computer system having multiple displays, communications, and DASD using the 80286, one problem is to allow long data transfers, which halt processor execution, while somehow still handling interrupts. Specifically, this means that the processor must be allowed to handle interrupts during long data transfers. This will allow service for time-critical interrupts like communications while still allowing large data transfers from disk. To be certain that interrupts will be processed rapidly, hardware was added to the interrupt controller. This hardware has the effect of changing the bus arbitration level for the processor when there is an interrupt. The higher bus arbitration level insures that the processor will be allowed to operate even if the interrupt occurs during a long data transfer.