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High Performance Address Translation Registers

IP.com Disclosure Number: IPCOM000034789D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Anthony, BO Kuhlman, CL [+details]

Abstract

The register arrangement includes high performance address translation registers which provide address translation with no increase in memory access time. Address translation registers (ATRs) are needed so the 80286 chip operating in real mode with an addressability of 1M can address memory space of up to 8M. High performance address translations are needed so the translation can be done without increasing the memory access time. Having a minimal memory access time is critical to the system performance. (Image Omitted) Address translation allows the 80286 chip to address up to 16MB of memory space even though only 20 bits of addressing are used. A typical implementation has ATRs which are loaded with the translated address.