Direct Memory Access for Multiple Requesting Computer Devices
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
A technique is described whereby cache memory implementation is provided for direct memory access (DMA) data fetches when multiple communication input/output (I/O) devices are attached to a common bus. Discussed are the efficiencies of accessing the I/O processor's (IOP) memory in sequential access modes so as to better utilize the bandwidth on a synchronous communication bus and to take advantage of dynamic random access memory (DRAM) page mode characteristics. (Image Omitted) As a background, subsystems such as shown in Fig. 1, are designed as an IOP intended for use with communication devices and protocols. In this subsystem, the memory can be accessed by using page mode and interleaving techniques so as to achieve a four-to-one speed advantage over accessing single word mode.