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Signal Synchronization, Latching and Arbitrary Priority Assignment When Two Signals Are Coincident

IP.com Disclosure Number: IPCOM000034803D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Leininger, JC [+details]

Abstract

This article describes a circuit arrangement which provides the means to synchronize two asynchronous signals by clocking them through three level-sensitive scan design (LSSD) latches to eliminate oscillations and metastability. If the two signals become active during the same half cycle, the priority will be determined by which half cycle the signals went active. Fig. 1 shows the latch and clock sequences necessary to accomplish the desired function. Latches 5 and 6 have clocks that are always active and data flushes through them without any latching taking place. Direct memory access (DMA) 1 request is clocked sequentially into latches 1, 2 and 4. Prior to latch 4 is an AND circuit 3 that will only allow latch 2 to be clocked into latch 4 if no DMA 2 cycle (latch 10) is present.