Temperature and Parameter Dependent Voltage Supply for Charge Buffered Logic Circuits
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
A technique is described whereby the internal voltage swing, and therefore the speed of charge buffered logic circuits, is maintained over a large temperature and parameter range through the use of voltage supply reference cells and distribution networks. (Image Omitted) A typical charged buffered logic (CBL) circuit, as shown in Fig. 1, is designed to achieve bipolar speed with CMOS compatible power. In the CBL circuit, the internal (base node) swing depends only on the power supply voltage and the VBE voltages of the NPN and PNP transistors. The uplevel of the internal base node (gate is on) is determined by the VBE1 of the NPN. The downlevel is determined by VB minus the VBE2 of the PNP transistor.